The display is generally constituted by pixel matrixes in horizontal and longitudinal directions. When the display performs displaying, the driving circuit outputs a drive signal to perform scanning to respective pixels row by row. In addition, in some displays, the driving circuit needs to output a multi-pulse drive signal. The multi-pulse drive signal has the characteristic that the drive signal of each row is transferred row by row by at least two signals with the same clock period, the same duty ratio and the same pulse number by taking the period of the drive signal as the delay. The driving circuit that generates such a drive signal is called a multi-pulse shift register.
As shown in FIG. 1, the gate drive signal of each stage in the multi-pulse shift register in the prior art is controlled and outputted by a multi-pulse output unit 101 and an advanced unit 102. The multi-pulse output unit 101 and the advanced unit 102 consist of gate driver on array (GOA) units of the same or similar structure. The output signal of the GOA unit constituting the multi-pulse output unit 101 serves as the input signal of the GOA unit constituting the advanced unit 102. The output signal of the GOA unit constituting the advanced unit 102 has the same waveform as the output signal of the GOA unit constituting the multi-pulse output unit 101, while being delayed for ½ clock period. The output signal of the GOA unit constituting the advanced unit 102 further serves as the input signal of the GOA unit constituting the next stage multi-pulse output unit. The output signal of the GOA unit constituting the next stage multi-pulse output unit has the same waveform as the output signal of the GOA unit constituting the current stage multi-pulse output unit, which is delayed for one clock period. Finally, a multi-pulse drive signal can be obtained by inputting the output signal of the GOA unit constituting the multi-pulse output unit into a corresponding gate line as a drive signal. In the multi-pulse shift register of the prior art, the drive signals of one stage gate line are controlled and outputted by two GOA units of the same or similar structure, thus resulting in a large area and great power consumption of the gate driving circuit in the prior art.